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functional block diagram external address bus external data bus dma bus serial ports sport 1 sport 0 memory program memory data memory programmable i/o flags byte dma controller timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data internal dma port a dsp microcomputer adsp-2181 features performance 25 ns instruction cycle time from 20 mhz crystal @ 5.0 volts 40 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 100 cycle recovery from power-down condition low power dissipation in idle mode integration adsp-2100 family code compatible, with instruction set extensions 80k bytes of on-chip ram, configured as 16k words on-chip program memory ram 16k words on-chip data memory ram dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 128-lead tqfp/128-lead pqfp system interface 16-bit internal dma port for high speed access to on-chip memory 4 mbyte memory interface for storage of data tables and program overlays 8-bit dma to byte memory for transparent program and data memory transfers i/o memory interface with 2048 locations supports parallel peripherals programmable memory strobe and separate i/o memory space permits glueless system design programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling ice-port? emulator interface supports debugging in final systems rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ice-port is a trademark of analog devices, inc. general description the adsp-2181 is a single-chip microcomputer optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsp-2181 combines the adsp-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the adsp-2181 integrates 80k bytes of on-chip memory con- figured as 16k words (24-bit) of program ram, and 16k words (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. the adsp-2181 is available in 128-lead tqfp and 128- lead pqfp packages. in addition, the adsp-2181 supports new instructions, which include bit manipulationsbit set, bit clear, bit toggle, bit test new alu constants, new multiplication instruction (x squared), biased rounding, result free alu operations, i/o memory trans- fers and global interrupt masking for increased flexibility. fabricated in a high speed, double metal, low power, cmos process, the adsp-2181 operates with a 25 ns instruction cycle time. every instruction can execute in a single processor cycle. the adsp-2181s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. in one processor cycle the adsp-2181 can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
rev. d adsp-2181 C2C this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive and/or transmit data through the internal dma port ? receive and/or transmit data through the byte dma port ? decrement timer development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, supports the adsp-2181. the system builder provides a high level method for defining the architecture of systems under development. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. a prom splitter generates prom programmer compatible files. the c compiler, based on the free software foundations gnu c compiler, generates adsp-2181 assembly source code. the source code debugger allows programs to be cor- rected in the c environment. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. the ez-kit lite is a hardware/software kit offering a complete development environment for the entire adsp-21xx family: an adsp-2181 evaluation board with pc monitor software plus assembler, linker, simulator, and prom splitter software. the adsp-218x ez-kit lite is a low-cost, easy to use hard- ware platform on which you can quickly get started with your dsp software design. the ez-kit lite includes the following features: ? 33 mhz adsp-2181 ? full 16-bit stereo audio i/o with ad1847 soundport ? codec ? rs-232 interface to pc with windows 3.1 control software ? stand-alone operation with socketed eprom ? ez-ice ? connector for emulator control ? dsp demo programs the adsp-218x ez-ice emulator aids in the hardware debug- ging of adsp-218x systems. the emulator consists of hard- ware, host computer resident software and the target board connector. the adsp-218x integrates on-chip emulation sup- port with a 14-pin ice-port interface. this interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other adsp-2100 family ez-ices. the adsp-218x device need not be rem oved from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice conne ctor, emulation can be supported in final board designs. the ez-ice performs a full range of functions, including: ? in-target operation ? up to 20 breakpoints ? single-step or full-speed operation ? registers and memory values can be examined and altered ? pc upload and download functions ? instruction-level emulation of program booting and execution ? complete assembly and disassembly of instructions ? c source-level debugging see the designing an ez-ice-compatible target system sec- tion of this data sheet for exact specifications of the ez -ice target board connector. additional information this data sheet provides a general overview of adsp-2181 functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family users manual, third edition . for more information about the development tools, refer to the adsp-2100 family development tools data sheet . architecture overview the adsp-2181 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single pro- cessor cycle. the adsp-2181 assembly language uses an alge- braic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. figure 1 is an overall block diagram of the adsp-2181. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provi- sions to support multiprecision computations. the alu per- forms a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arith- metic shifts, normalization, denormalization and derive expo- nent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating- point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa- tional units. the sequencer supports conditional jumps, subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the adsp-2181 executes looped code with zero over- head; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the adsp-2181 to fetch two operands in a single cycle, one from program memory and one from data memory. the ez-ice and soundport are registered trademarks of analog devices, inc.
adsp-2181 C3C rev. d adsp-2181 can fetch an operand from program memory and the next instruction in the same cycle. in addition to the address and data bus for external memory connection, the adsp-2181 has a 16-bit internal dma port (idma port) for connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with program- mable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh and bg ). one execution mode (go mode) allows the adsp-2181 to con- tinue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the adsp-2181 can respond to 13 possible interrupts, eleven of which are accessible at any given time. there can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial inter- face with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the adsp-2181 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n pro- cessor cycles, where n is a scaling value stored in an 8-bit regis- ter (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the adsp-2181 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the adsp-2181 sports. refer to the adsp-2100 family users manual, third edition for further details. ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. output regs alu output regs mac timer input regs input regs adsp-2181 integration data address generator #1 data address generator #2 21xx core pma bus dma bus pmd bus instruction register program sequencer bus exchange dmd bus program sram 16k 3 24 data sram 16k 3 16 byte dma controller mux 14 14 24 16 dmd bus pma bus dma bus pmd bus input regs shifter output regs input regs mac output regs input regs alu output regs r bus 16 transmit reg receive reg serial port 0 transmit reg receive reg serial port 0 companding circuitry 5 5 internal dma port interrupts power- down control logic 2 8 3 mux programmable i/o flags 14 external address bus external data bus 16 4 24 figure 1. adsp-2181 block diagram
rev. d adsp-2181 C4C ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. pin descriptions the adsp-2181 is available in 128-lead tqfp and 128-lead pqfp packages. pin function descriptions # pin of input/ name(s) pins output function address 14 o address output pins for program, data, byte, and i/o spaces data 24 i/o data i/o pins for program and data memory spaces (8 msbs are also used as byte space addresses) reset 1 i processor reset input irq2 1 i edge- or level-sensitive interrupt request irql0 , irql1 2 i level-sensitive interrupt requests irqe 1 i edge-sensitive interrupt request br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output pms 1 o program memory select output dms 1 o data memory select output bms 1 o byte memory select output ioms 1 o i/o space memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output mmap 1 i memory map select input bmode 1 i boot option control input clkin, xtal 2 i clock or quartz crystal input # pin of input/ name(s) pins output function clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1 5 i/o serial port 1 or two external irq s, flag in and flag out ird , iwr 2 i idma port read/write inputs is 1 i idma port select ial 1 i idma port address latch enable iad 16 i/o idma port address/data bus iack 1 o idma port access ready acknowledge pwd 1 i power-down control pwdack 1 o power-down control fl0, fl1, fl2 3 o output flags pf7:0 8 i/o programmable i/o pins ee 1 * (emulator only*) ebr 1 * (emulator only*) ebg 1 * (emulator only*) ereset 1 * (emulator only*) ems 1 * (emulator only*) eint 1 * (emulator only*) eclk 1 * (emulator only*) elin 1 * (emulator only*) elout 1 * (emulator only*) gnd 11 C ground pins vdd 6 C power supply pins *these adsp-2181 pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the adsp-2181 provides four dedicated external interrupt input pins, irq2 , irql0 , irql1 and irqe . in addition, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the adsp- 2181 also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable (except power down and reset). the irq2 , irq0 and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level- sensitive and irqe is edge sensitive. the priorities and vector addresses of all interrupts are shown in table i.
adsp-2181 C5C rev. d table i. interrupt priority and interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 ( highest priority ) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 ( lowest priority ) interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. inter- rupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. the adsp-2181 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nest- ing and defines the irq0 , irq1 and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an external edge-sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are external level-sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. the following instructions allow global enable or disable servic- ing of the interrupts (including power down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the adsp-2181 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? power-down ? idle ? slow idle the clkout pin may also be disabled to reduce external power dissipation. power-down the adsp-2181 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. here is a brief list of power- down features. for detailed information about the power- down feature, refer to the adsp-2100 family users manual , third edition, system interface chapter. ? quick recovery from power-down. the processor begins executing instructions in as few as 100 clkin cycles. ? support for an externally generated ttl or cmos processor clock. the external clock can continue running during power-down without affecting the lowest power rating and 100 clkin cycle recovery. ? support for crystal operation includes disabling the oscil- lator to save power (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabi- lize), and letting the oscillator run to allow 100 clkin cycle start up. ? power-down is initiated by either the power-down pin ( pwd ) or the software power-down force bit. ? interrupt support allows an unlimited number of instruc- tions to be executed before optionally powering down. the power-down interrupt also can be used as a non- maskable, edge-sensitive interrupt. ? context clear/save control allows the processor to con- tinue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power- down. ? power-down acknowledge pin indicates when the proces- sor has entered power-down. idle when the adsp-2181 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. slow idle the idle instruction is enhanced on the adsp-2181 to let the processors internal clock signal be slowed, further reducing power consumption. the reduced clock fre- quency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle in- struction. the format of the instruction is idle (n); where n = 16, 32, 64 or 128. this instruction keeps the processor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction.
rev. d adsp-2181 C6C when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to in- coming interrupts. the one-cycle response time of the standard idle state is increased by n , the clock divisor. when an enabled interrupt is received, the adsp-2181 will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64 or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 2 shows a typical basic system configuration with the adsp-2181, two serial devices, a byte-wide eprom, and op- tional external program and data overlay memories. program- mable wait state generation allows the processor to connect easily to slow peripheral devices. the adsp-2181 also provides four external interrupts and two serial ports or six external inter- rupts and one serial port. 1/2x clock or crystal serial device serial device 16 a0-a21 data cs byte memory i/o space (peripherals) cs data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments d 23-0 a 13-0 d 23-8 a 10-0 d 15-8 d 23-16 a 13-0 14 24 sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 iad15-0 idma port fl0-2 pf0-7 clkin xtal addr13-0 data23-0 bms ioms adsp-2181 rd wr irq2 irqe irql0 irql1 pms dms cms br bg bgh pwd pwdack ird iwr is ial iack sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi system interface or m controller figure 2. adsp-2181 basic system configuration clock signals the adsp-2181 can be clocked by either a crystal or a ttl- compatible clock signal. the clkin input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. the only exception is while the processor is in the power- down state. for additional information, refer to chapter 9, adsp-2100 family users manual, third edition , for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is con- nected to the processors clkin input. when an external clock is used, the xtal input must be left unconnected. the adsp-2181 uses an input clock with a frequency equal to half the instruction rate; a 20.00 mhz input clock yields a 25 ns processor cycle (which is equivalent to 40 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the adsp-2181 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors con nected as shown in figure 3. capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processors cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. clkin clkout xtal dsp figure 3. external crystal connections reset the reset signal initiates a master reset of the adsp-2181. the reset signal must be asserted during the power-up se- quence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is ap- plied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the mini- mum pulse width specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit to generate your reset signal, the use of an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting (mmap = 0), the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
adsp-2181 C7C rev. d table ii. pmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 0 13 lsbs of ad dress overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of address overlay 2 between 0x2000 and 0x3fff this organization provides for two external 8k overlay segments using only the normal 14 address bits. this allows for simple program overlays using one of the two external segments in place of the on-chip memory. care must be taken in using this overlay space in that the processor core (i.e., the sequencer) does not take into account the pmovlay register value. for example, if a loop operation was occurring on one of the exter- nal overlays and the program changes to another external over- lay or internal memory, an incorrect loop operation could occur. in addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack. for adsp-2100 family compatibility, mmap = 1 is allowed. in this mode, booting is disabled and overlay memory is dis- abled (pmovlay must be 0). figure 5 shows the memory map in this configuration. internal 8k (pmovlay = 0, mmap = 1) 0x3fff 0x2000 0x1fff 8k external 0x0000 program memory address figure 5. program memory (mmap = 1) data memory the adsp-2181 has 16,352 16-bit words of internal data memory. in addition, the adsp-2181 allows the use of 8k external memory overlays. figure 6 shows the organization of the data memory. 8k internal (dmovlay = 0) or external 8k (dmovlay = 1, 2) internal 8160 words data memory address 32 memoryC mapped registers 0x3fff 0x3feo 0x3fdf 0x2000 0x1fff 0x0000 figure 6. data memory memory architecture the adsp-2181 provides a variety of memory and peripheral interface options. the key functional groups are program memory, data memory, byte memory and i/o. program memory is a 24-bit-wide space for storing both instruction opcodes and data. the adsp-2181 has 16k words of program memory ram on chip and the capability of access- ing up to two 8k external memory overlay spaces using the external data bus. both an instruction opcode and a data value can be read from on-chip program memory in a single cycle. data memory is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the adsp-2181 has 16k words on data memory ram on chip, consisting of 16,352 user-accessible locations and 32 memory- mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus. byte memory provides access to an 8-bit wide memory space through the byte dma (bdma) port. the byte memory inter- face provides access to 4 mbytes of memory by utilizing eight data lines as additional address lines. this gives the bdma port an effective 22-bit address range. on power-up, the dsp can automatically load bootstrap code from byte memory. i/o space allows access to 2048 locations of 16-bit-wide data. it is intended to be used to communicate with parallel periph- eral devices such as data converters and external registers or latches. program memory the adsp-2181 contains a 16k 24 on-chip program ram. the on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. in addition, the adsp-2181 allows the use of 8k external memory overlays. the program memory space organization is controlled by the mmap pin and the pmovlay register. normally, the adsp- 2181 is configured with mmap = 0 and program memory orga- nized as shown in figure 4. 8k internal (pmovlay = 0, mmap = 0) or external 8k (pmovlay = 1 or 2, mmap = 0) 0x3fff 0x2000 0x1fff 8k internal 0x0000 program memory address figure 4. program memory (mmap = 0) there are 16k words of memory accessible internally when the pmovlay register is set to 0. when pmovlay is set to something other than 0, external accesses occur at addresses 0x2000 through 0x3fff. the external address is generated as shown in table ii.
rev. d adsp-2181 C8C the cms pin functions like the other memory select signals, with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits, except the bms bit, default to 1 at reset. byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the byte memory space consists of 256 pages, each of which is 16k 8. the byte memory space on the adsp-2181 supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally, and steals only one dsp cycle per 8-, 16- or 24-bit word transferred. the bdma circuit supports four different data formats which are selected by the btype register field. the appropriate num- ber of 8-bit accesses are done from the byte memory space to build the word size selected. table v shows the data formats supported by the bdma circuit. table v. internal btype memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the start- ing page for the external byte memory space. the bdir register field selects the direction of the transfer. finally the 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is gener- ated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory, regardless of the values of mmap, pmovlay or dmovlay. there are 16,352 words of memory accessible internally when the dmovlay register is set to 0. when dmovlay is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1fff. the external address is generated as shown in table iii. table iii. dmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 0 13 lsbs of address overlay 1 between 0x0000 and 0x1fff 2 external 1 13 lsbs of address overlay 2 between 0x0000 and 0x1fff this organization allows for two external 8k overlays using only the normal 14 address bits. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. i/o space the adsp-2181 supports an additional external memory space called i/o space. this space is designed to support simple con- nections to peripherals or to bus interface asic data registers. i/o space supports 2048 locations. the lower eleven bits of the external address bus are used; the upper three bits are unde- fined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated 3-bit wait state registers, iowait0-3, which specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges as shown in table iv. table iv. address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 composite memory select ( cms ) the adsp-2181 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can combine their functionality. when set, each bit in the cmssel register, causes the cms signal to be asserted when the selected memory select is as- serted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory; use either dms or pms as the additional address bit.
adsp-2181 C9C rev. d table vi. boot summary table mmap bmode booting method 0 0 bdma feature is used in default mode to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. 0 1 idma feature is used to load any inter- nal memory as desired. program execu- tion is held off until internal program memory location 0 is written to. 1 x bootstrap features disabled. program execution immediately starts from location 0. bdma booting when the bmode and mmap pins specify bdma booting (mmap = 0, bmode = 0), the adsp-2181 initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma boot- ing is specified: the bdir, bmpage, biad and bead regis- ters are set to 0, the btype register is set to 0 to specify program memory 24 bit words, and the bwcount register is set to 32. this causes 32 words of on-chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the adsp-2100 family development software (revision 5.02 and later) fully supports the bdma booting feature and can generate byte memory space compatible boot code. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. idma booting the adsp-2181 can also boot programs through its internal dma port. if bmode = 1 and mmap = 0, the adsp-2181 boots from the idma port. idma feature can load as much on- chip memory as desired. program execution is held off until on- chip program memory location 0 is written to. the adsp-2100 family development software (revision 5.02 and later) can generate idma compatible boot code. bus request and bus grant the adsp-2181 can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the adsp-2181 is not performing an external memory access, then it responds to the active br input in the following processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory ac- cesses. the bdma context reset bit (bcr) controls whether the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor and start execution at address 0 when the bdma accesses have completed. internal memory dma port (idma port) the idma port provides an efficient means of communication between a host system and the adsp-2181. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot, however, be used to write to the dsps memory- mapped control registers. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is completely asynchronous and can be written to while the adsp-2181 is operating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this in- creases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14- bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location; the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register. once the address is stored, data can either be read from or written to the adsp-2181s on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the adsp-2181 that a particular transaction is required. in either case, there is a one-processor- cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. bootstrap loading (booting) the adsp-2181 has two mechanisms to allow automatic load- ing of the on-chip program memory after reset. the method for booting after reset is controlled by the mmap and bmode pins as shown in table vi.
rev. d adsp-2181 C10C if go mode is enabled, the adsp-2181 will not halt program execution until it encounters an instruction that requires an external memory access. if the adsp-2181 is performing an external memory access when the external device asserts the br signal, then it will not three-state the memory interfaces or assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program execution from the point where it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the adsp-2181 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. the other device can re- lease the bus by deasserting bus request. once the bus is re- leased, the adsp-2181 deasserts bg and bgh and executes the external memory access. flag i/o pins the adsp-2181 has eight general purpose programmable in- put/output flag pins. they are controlled by two memory mapped registers. the pftype register determines the direc- tion, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the adsp-2181s clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the adsp-2181 has five fixed-mode flags, flag_in, flag_out, fl0, fl1 and fl2. fl0-fl2 are dedicated output flags. flag_in and flag_out are available as an alternate configuration of sport1. instruction set description the adsp-2181 assembly language instruction set has an algebraic syntax that was designed for ease of coding and read- ability. the assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize on-chip memory and conform to the adsp- 2181s interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the adsp-2181 has on-chip emulation support and an ice- port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ice s in-circuit probe, a 14-pin plug. the ice-port interface consists of the following adsp-2181 pins: ebr ems elin ebg eint elout ereset eclk ee these adsp-2181 pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull- down resistors. the traces for these signals between the adsp- 2181 and the connector must be kept as short as possible, no longer than three inches. the following pins are also used by the ez-ice: br bg gnd reset the ez-ice uses the ee (emulator enable) signal to take con- trol of the adsp-2181 in the target system. this causes the processor to use its ereset , ebr and ebg pins instead of the reset , br and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to the target system via a ribbon cable and a 14-pin female plug. the ribbon cable is 10 inches in length with one end fixed to the ez-ice. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 7. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector. 12 3 4 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 7. target board connector for ez-ice
adsp-2181 C11C rev. d the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tionyou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 x 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie and samtec. target memory interface for your target system to be compatible with the ez-ice emu- lator, it must comply with the memory interface guidelines listed below. pm, dm, bm, iom and cm design your program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom) and composite memory (cm) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the dsps data sheet. the performance of the ez-ice may approach published worst case specification for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst case chip specifica- tion for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. de- pending on the severity of the specification violation, you may have trouble manufacturing your system as dsp components statistically vary in switching characteristic and timing require- ments within published limits. restriction: all memory strobe signals on the adsp-2181 ( rd , wr , pms , dms , bms , cms and ioms ) used in your target system must have 10 k w pull-up resistors connected when the ez-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals changes. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay be- tween your target circuitry and the dsp on the reset signal. ? ez-ice emulation introduces an 8 ns propagation delay be- tween your target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emulator space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsps external memory bus only if bus grant ( bg ) is asserted by the ez-ice boards dsp. target architecture file the ez-ice software lets you load your program in its linked (executable) form. the ez-ice pc program can not load sec- tions of your executable located in boot pages (by the linker). with the exception of boot page 0 (loaded into pm ram), all sections of your executable mapped into boot pages are not loaded. write your target architecture file to indicate that only pm ram is available for program storage, when using the ez-ice softwares loading feature. data can be loaded to pm ram or dm ram.
adsp-2181Cspecifications recommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 4.5 5.5 4.5 5.5 v t amb ambient operating temperature 0 +70 C40 +85 c electrical characteristics k/b grades parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max v in = 0 v 10 m a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 m a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 10 m a i dd supply current (idle) 9 @ v dd = 5.0 t amb = +25 c t ck = 34.7 ns 12 ma t ck = 30 ns 13 ma t ck = 25 ns 15 ma i dd supply current (dynamic) 10 @ v dd = 5.0 t amb = +25 c t ck = 34.7 ns 11 65 ma t ck = 30 ns 11 73 ma t ck = 25 ns 11 85 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c8pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c8pf notes 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2-0, bgh . 5 although specified for ttl outputs, all adsp-2186 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0Ca13, d0Cd23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, pf0Cpf7. 8 0 v on br , clkin inactive. 9 idle refers to adsp-2181 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 12 applies to tqfp and pqfp package types. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. C12C rev. d
adsp-2181 C13C rev. d esd sensitivity the adsp-2181 is an esd (electrostatic discharge) sensitive device. electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subjected to high energy electrostatic discharges. the adsp-2181 features proprietary esd protection circuitry to dissipate high energy discharges (human body model). per method 3015 of mil-std-883, the adsp-2181 has been classified as a class 1 device. proper esd precautions are recommended to avoid performance degradation or loss of function- ality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. timing parameters general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the proc essor will do in a given circumstance. you can also use switch- ing characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. memory timing specifications the table below shows common memory device specifications and the corresponding adsp-2181 timing parameters, for your convenience. memory adsp-2181 timing device timing parameter specification parameter definition address setup to t asw a0Ca13, xms setup before write start wr low address setup to t aw a0Ca13, xms setup before write end wr deasserted address hold time t wra a0Ca13, xms hold after wr deasserted data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, xms to data valid xms = pms , dms , bms , cms , ioms . frequency dependency for timing specifications t ck is defined as 0.5t cki . the adsp-2181 uses an input clock with a frequency equal to half the instruction rate: a 16.67 mhz input clock (which is equivalent to 60 ns) yields a 30 ns proces- sor cycle (equivalent to 33 mhz). t ck values within the range of 0.5t cki period should be substituted for all relevant timing pa- rameters to obtain the specification value. example: t ckh = 0.5t ck C 7 ns = 0.5 (25 ns) C 7 ns = 8 ns absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) tqfp . . . . . . . . . . . . . . . . +280 c lead temperature (5 sec) pqfp . . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device
rev. d adsp-2181 C14C parameter min max unit clock signals and reset timing requirements : t cki clkin period 50 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristics : t ckl clkout width low 0.5t ck C 7 ns t ckh clkout width high 0.5t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement : t rsp reset width low 5t ck 1 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time). t ckoh t cki t ckih t ckil t ckh t ckl t mh t ms clkin clkout pf(2:0) * reset * pf2 is mode c, pf1 is mode b, pf0 is mode a figure 8. clock signals
adsp-2181 C15C rev. d parameter min max unit interrupts and flag timing requirements : t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25t ck + 15 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 5 0.5t ck C 7 ns t fod flag output delay from clkout low 5 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the users manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , i rql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, flag_out4. t fod t foh t ifh t ifs clkout flag outputs irq x fi pfx figure 9. interrupts and flags
rev. d adsp-2181 C16C parameter min max unit bus request/grant timing requirements : t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristics : t sd clkout high to xms , 0.25t ck + 10 ns rd , wr disable t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 0.25t ck C 4 ns t sdbh xms , rd , wr disable to bgh low 2 0ns t seh bgh high to xms , rd , wr enable 2 0ns notes xms = pms , dms , cms , ioms , bms . 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family users manual, third edition for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. clkout t sd t sdb t se t sec t sdbh t seh t bs br t bh clkout pms , dms bms , rd wr bg bgh figure 10. bus requestCbus grant
adsp-2181 C17C rev. d parameter min max unit memory read timing requirements : t rdd rd low to data valid 0.5t ck C 9 + w ns t aa a0Ca13, xms to data valid 0.75t ck C 10.5 + w ns t rdh data hold from rd high 0 ns switching characteristics : t rp rd pulsewidth 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 7 ns t asr a0Ca13, xms setup before rd low 0.25t ck C 4 ns t rda a0Ca13, xms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0Ca13 d t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms , ioms , cms rd wr figure 11. memory read
rev. d adsp-2181 C18C parameter min max unit memory write switching characteristics : t dw data setup before wr high 0.5t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulsewidth 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, xms setup before wr low 0.25t ck C 4 ns t ddr data disable before wr or rd low 0.25t ck C 4 ns t cwr clkout high to wr low 0.25t ck C 5 0.25 t ck + 7 ns t aw a0Ca13, xms , setup before wr deasserted 0.75t ck C 9 + w ns t wra a0Ca13, xms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms , bms , cms , ioms rd wr figure 12. memory write
adsp-2181 C19C rev. d parameter min max unit serial ports timing requirements : t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclk in width 20 ns switching characteristics : t cc clkout high to sclk out 0.25t ck 0.25t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout sclk tfs out rfs out dt alternate frame mode t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv multichannel mode, frame delay 0 (mfd = 0) dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp tfs in rfs in alternate frame mode t rdv multichannel mode, frame delay 0 (mfd = 0) t tdv t tde figure 13. serial ports
rev. d adsp-2181 C20C parameter min max unit idma address latch timing requirements : t ialp duration of address latch 1, 2 10 ns t iasu iad15C0 address setup before address latch end 2 5ns t iah iad15C0 address hold after address latch end 2 2ns t ika iack low before start of address latch 1 0ns t ials start of write or read after address latch end 2, 3 3ns notes 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 start of write or read = is low and iwr low or ird low. t ika iad15C0 iack ial is ird iwr or t ialp t iasu t iah t ials figure 14. idma address latch
adsp-2181 C21C rev. d parameter min max unit idma write, short write cycle timing requirements : t ikw iack low before start of write 1 0ns t iwp duration of write 1, 2 15 ns t idsu iad15C0 data setup before end of write 2, 3, 4 5ns t idh iad15C0 data hold after end of write 2, 3, 4 2ns switching characteristic : t ikhw start of write to iack high 15 ns notes 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . iad15C0 data t ikhw t ikw t idsu iack t iwp t idh is iwr figure 15. idma write, short write cycle
rev. d adsp-2181 C22C parameter min max unit idma write, long write cycle timing requirements : t ikw iack low before start of write 1 0ns t iksu iad15C0 data setup before iack low 2, 3 0.5t ck + 10 ns t ikh iad15C0 data hold after iack low 2, 3 2ns switching characteristics : t iklw start of write to iack low 4 1.5t ck ns t ikhw start of write to iack high 15 ns notes 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the users manual. iad15C0 data t ikhw t ikw iack is iwr t iklw t ikh t iksu figure 16. idma write, long write cycle
adsp-2181 C23C rev. d parameter min max unit idma read, long read cycle timing requirements : t ikr iack low before start of read 1 0ns t irp duration of read 15 ns switching characteristics : t ikhr iack high after start of read 1 15 ns t ikds iad15C0 data setup before iack low 0.5t ck C 10 ns t ikdh iad15C0 data hold after end of read 2 0ns t ikdd iad15C0 data disabled after end of read 2 12 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 15 ns t irdh1 iad15C0 previous data hold after start of read (dm/pm1) 3 2t ck C 5 ns t irdh2 iad15C0 previous data hold after start of read (pm2) 4 t ck C 5 ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. 3 dm read or first half of pm read. 4 second half of pm read. t irp t ikr previous data read data t ikhr t ikds t irdv t irdh t ikdd t irde t ikdh iad15C0 iack is ird figure 17. idma read, long read cycle
rev. d adsp-2181 C24C parameter min max unit idma read, short read cycle timing requirements : t ikr iack low before start of read 1 0ns t irp duration of read 15 ns switching characteristics : t ikhr iack high after start of read 1 15 ns t ikdh iad15C0 data hold after end of read 2 0ns t ikdd iad15C0 data disabled after end of read 2 12 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 15 ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iad15C0 iack is ird figure 18. idma read, short read cycle
adsp-2181 C25C rev. d output drive currents figure 19 shows typical i-v characteristics for the output drivers of the adsp -2181. the curves represent the current drive capability of the output drivers as a function of output voltage. source voltage C volts source current C ma 120 C80 01 6 2345 100 0 C20 C40 C60 80 60 20 40 5.5v, C40 8 c 5.0v, +25 8 c 4.5v, +85 8 c 4.5v, +85 8 c 5.0v, +25 8 c 5.5v, C40 8 c figure 19. typical drive currents power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 30 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 20). temperature C c 1000 1 100 10 current (log scale) C m a 585 15 25 35 45 55 65 75 C5 v dd = 5.5v v dd = 5.0v v dd = 4.5v notes: 1. reflects adsp-2181 operation in lowest power mode. (see system interface" chapter of the adsp-2100 family user's manual, third edition, for details.) 2. current reflects device operating with no output loads. figure 20. power-down supply current (typical) ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 5 2 v 33.3 mhz = 66.6 mw data output, wr 9 10 pf 5 2 v 16.67 mhz = 37.5 mw rd 1 10 pf 5 2 v 16.67 mhz = 4.2 mw clkout 1 10 pf 5 2 v 33.3 mhz = 8.3 mw 116.6 mw total power dissipation for this example is p int + 116.6 mw. 1/t ck C mhz power (p int ) C mw 220 30 32 42 34 36 38 40 420 370 320 270 570 470 520 2181 power, internal 1, 3, 4 v dd = 5.5v v dd = 5.0v v dd = 4.5v 410mw 325mw 250mw 550mw 425mw 330mw 28 power (p idle ) C mw 1/t ck C mhz 100 40 30 32 42 34 36 38 40 70 60 50 90 80 30 power, idle 1, 2, 3 v dd = 5.5v v dd = 5.0v v dd = 4.5v 77mw 60mw 45mw 95mw 75mw 54mw 28 1/t ck C mhz power (p idle n ) C mw 80 30 30 32 42 34 36 38 40 75 50 45 40 35 70 65 55 60 power, idle n modes 3 idle idle (16) idle (128) 60mw 35mw 34mw 39mw 37mw 75mw 28 valid for all temperature grades. 4 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6 and 20% are idle instructions. 3 typical power dissipation at 5.0v v dd and 25 8 c except where specified. 2 idle refers to adsp-2181 state of operation during execution of idle 1 power reflects device operating with no output loads. instruction. deasserted pins are driven to either v dd or gnd. figure 21. power vs. frequency
rev. d adsp-2181 C26C capacitive loading figures 22 and 23 show the capacitive loading characteristics of the adsp-2181. c l C pf rise time (0.4vC2.4v) C ns 0 50 100 150 200 250 25 15 10 5 0 20 figure 22. range of output rise time vs. load capaci- tance, c l (at maximum ambient operating temperature) c l C pf 14 0 valid output delay or hold C ns 50 100 150 250 200 12 4 2 C2 10 8 16 6 C4 0 figure 23. range of output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low volt- age level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the fol- lowing equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. 1.5v input or output 1.5v figure 24. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 25. output enable/disable to output pin 50pf +1.5v i oh i ol figure 26. equivalent device loading for ac measure- ments (including all fixtures)
adsp-2181 C27C rev. d environmental conditions ambient temperature rating: t amb =t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca tqfp 50 c/w 2 c/w 48 c/w pqfp 41 c/w 10 c/w 31 c/w
rev. d adsp-2181 C28C 128-lead tqfp package pinout 1 128 is 65 64 39 38 103 102 top view (pins down) ial pf3 pf2 pf1 pf0 gnd a0 a1 a2 a3 a4 a5 a6 a7 xtal clkin clkout gnd a8 a9 a10 a11 a12 a13 mmap wr vdd gnd bmode fl0 dt0 tfs0 rfs0 dr0 sclk0 dr1/fi sclk1 fl1 fl2 rfs1/ irq0 dt1/f0 tfs1/ irq1 gnd pwdack gnd vdd ereset gnd d23 d22 d21 d20 d19 gnd d18 d17 d16 d15 d14 d13 d12 d11 gnd d10 d9 d8 d7 d6 d5 d4 d3 gnd d2 d1 d0 elin eclk elout vdd vdd iad1 pf4 pf5 pf6 pf7 iad0 iad11 iad12 iad13 iad14 iad10 iad9 gnd iad15 ird iad4 iad5 iad6 iad7 iad3 iad2 iad8 gnd vdd vdd rd ioms bms dms cms pms irqe pwd irq2 iack bgh irql0 reset ee ems irql1 eint ebr br iwr ebg bg
adsp-2181 C29C rev. d tqfp pin configurations tqfp pin tqfp pin tqfp pin tqfp pin number name number name number name number name 1 ial 33 a12 65 eclk 97 d19 2 pf3 34 a13 66 elout 98 d20 3 pf2 35 irqe 67 elin 99 d21 4 pf1 36 mmap 68 eint 100 d22 5 pf0 37 pwd 69 ebr 101 d23 6 wr 38 irq2 70 br 102 gnd 7 rd 39 bmode 71 ebg 103 iwr 8 ioms 40 pwdack 72 bg 104 ird 9 bms 41 iack 73 vdd 105 iad15 10 dms 42 bgh 74 d0 106 iad14 11 cms 43 vdd 75 d1 107 iad13 12 gnd 44 gnd 76 d2 108 iad12 13 vdd 45 irql0 77 d3 109 iad11 14 pms 46 irql1 78 d4 110 iad10 15 a0 47 fl0 79 gnd 111 iad9 16 a1 48 fl1 80 d5 112 iad8 17 a2 49 fl2 81 d6 113 iad7 18 a3 50 dt0 82 d7 114 iad6 19 a4 51 tfs0 83 d8 115 vdd 20 a5 52 rfs0 84 d9 116 gnd 21 a6 53 dr0 85 d10 117 iad5 22 a7 54 sclk0 86 d11 118 iad4 23 xtal 55 dt1/f0 87 d12 119 iad3 24 clkin 56 tfs1/ irq1 88 d13 120 iad2 25 gnd 57 rfs1/ irq0 89 d14 121 iad1 26 clkout 58 gnd 90 gnd 122 iad0 27 gnd 59 dr1/fi 91 vdd 123 pf7 28 vdd 60 sclk1 92 gnd 124 pf6 29 a8 61 ereset 93 d15 125 pf5 30 a9 62 reset 94 d16 126 pf4 31 a10 63 ems 95 d17 127 gnd 32 a11 64 ee 96 d18 128 is
rev. d adsp-2181 C30C 128-lead pqfp package pinout 128l pqfp (28mm x 28mm) 1 128 97 96 65 64 33 32 top view (pins down) pf0 gnd a0 a1 a2 a3 a4 a5 a6 a7 xtal clkin clkout gnd a8 a9 a10 a11 a12 a13 mmap gnd vdd vdd wr ioms pms cms dms bms rd irqe pwdack bmode gnd fl0 rfs1/ irq0 gnd dr1/fi sclk1 ee eclk elout fl1 fl2 dt0 tfs0 rfs0 dr0 sclk0 dt1/f0 tfs1/ irq1 elin vdd pwd irq2 iack eint ems reset ereset irql0 bgh irql1 d22 d21 d20 d19 gnd d18 d17 d16 d15 d14 d13 d12 d11 gnd d10 d9 d8 d7 d6 d5 d4 d3 gnd d2 d1 d0 vdd vdd bg ebg br ebr gnd is ial gnd gnd d23 iad11 iad12 iad13 iad15 pf4 pf5 pf6 iad5 iad14 iad6 iad7 iad8 iad10 iad9 iad4 pf7 iad0 iad1 iad3 iad2 pf1 pf2 pf3 vdd ird iwr
adsp-2181 C31C rev. d pqfp pin configurations pqfp pin pqfp pin pqfp pin pqfp pin number name number name number name number name 1 pf0 33 pwd 65 ebr 97 d23 2 wr 34 irq2 66 br 98 gnd 3 rd 35 bmode 67 ebg 99 iwr 4 ioms 36 pwdack 68 bg 100 ird 5 bms 37 iack 69 vdd 101 iad15 6 dms 38 bgh 70 d0 102 iad14 7 cms 39 vdd 71 d1 103 iad13 8 gnd 40 gnd 72 d2 104 iad12 9vdd 41 irql0 73 d3 105 iad11 10 pms 42 irql1 74 d4 106 iad10 11 a0 43 fl0 75 gnd 107 iad9 12 a1 44 fl1 76 d5 108 iad8 13 a2 45 fl2 77 d6 109 iad7 14 a3 46 dt0 78 d7 110 iad6 15 a4 47 tfs0 79 d8 111 vdd 16 a5 48 rfs0 80 d9 112 gnd 17 a6 49 dr0 81 d10 113 iad5 18 a7 50 sclk0 82 d11 114 iad4 19 xtal 51 dt1/fo 83 d12 115 iad3 20 clkin 52 tfs1/ irq1 84 d13 116 iad2 21 gnd 53 rfs1/ irq0 85 d14 117 iad1 22 clkout 54 gnd 86 gnd 118 iad0 23 gnd 55 dr1/fi 87 vdd 119 pf7 24 vdd 56 sclk1 88 gnd 120 pf6 25 a8 57 ereset 89 d15 121 pf5 26 a9 58 reset 90 d16 122 pf4 27 a10 59 ems 91 d17 123 gnd 28 a11 60 ee 92 d18 124 is 29 a12 61 eclk 93 d19 125 ial 30 a13 62 elout 94 d20 126 pf3 31 irqe 63 elin 95 d21 127 pf2 32 mmap 64 eint 96 d22 128 pf1
rev. d adsp-2181 C32C ordering guide ambient instruction temperature rate package package part number range (mhz) description options* adsp-2181kst-115 0 c to +70 c 28.8 128-lead tqfp st-128 adsp-2181bst-115 C40 c to +85 c 28.8 128-lead tqfp st-128 adsp-2181ks-115 0 c to +70 c 28.8 128-lead pqfp s-128 adsp-2181bs-115 C40 c to +85 c 28.8 128-lead pqfp s-128 adsp-2181kst-133 0 c to +70 c 33.3 128-lead tqfp st-128 ADSP-2181BST-133 C40 c to +85 c 33.3 128-lead tqfp st-128 adsp-2181ks-133 0 c to +70 c 33.3 128-lead pqfp s-128 adsp-2181bs-133 C40 c to +85 c 33.3 128-lead pqfp s-128 adsp-2181kst-160 0 c to +70 c 40 128-lead tqfp st-128 adsp-2181ks-160 0 c to +70 c 40 128-lead pqfp s-128 *s = plastic quad flatpack (pqfp), st = plastic thin quad flatpack (tqfp). outline dimensions dimensions shown in mm and (inches). 128-lead metric plastic quad flatpack (pqfp) (s-128) 1 32 33 102 128 103 65 64 top view (pins down) 0.45 (0.018) 0.30 (0.012) 0.87 (0.034) 0.73 (0.029) 31.45 (1.238) 30.95 (1.219) 28.10 (1.106) 27.90 (1.098) 24.87 (0.979) 24.73 (0.974) 31.45 (1.238) 30.95 (1.219) 28.10 (1.106) 27.90 (1.098) 24.87 (0.979) 24.73 (0.974) seating plane 4.07 (0.160) max 1.03 (0.041) 0.65 (0.031) 0.10 (0.004) max 0.25 (0.010) min 3.67 (0.144) 3.17 (0.125) note: the actual position of each lead is within .20 (.008) from its ideal position when measured in the lateral direction. unless otherwise noted. 128-lead metric thin plastic quad flatpack (tqfp) (st-128) top view (pins down) 0.27 (0.011) 0.17 (0.007) 16.25 (0.640) 15.75 (0.620) 18.50 (0.728) typ 14.10 (0.555) 13.90 (0.547) 22.25 (0.876) 21.75 (0.856) 1 38 39 65 64 102 128 12.50 (0.492) typ 0.58 (0.023) 0.42 (0.017) 103 20.10 (0.792) 19.90 (0.783) seating plane 1.60 (0.063) typ 0.75 (0.030) 0.45 (0.018) 0.10 (0.004) max 1.50 (0.059) 1.30 (0.051) 0.15 (0.006) 0.05 (0.002) note: the actual position of each lead is within .08 (.0032) from its ideal position when measured in the lateral direction. unless otherwise noted. c2041cC3C3/98 printed in u.s.a.

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